1. Field of the Invention
The present invention relates to a semiconductor device having a vertical double diffused MOS transistor with a trench gate structure and a method for manufacturing the same.
2. Description of Related Art
For example, as a structure for increasing fineness and lowering on-resistance of a power device, a trench gate structure is known. In the field of power MOSFETs, employment of the trench gate structure has become mainstream.
FIG. 5 is a perspective view illustrating vertical double diffused MOSFET (VDMOSFET).
On an N+-type substrate 101, an N−-type layer 102 is laminated. On this N−-type layer 102, a P−-type layer 103 is laminated. On the P−-type layer 103, an N+-type region 104 and a P+-type region 105 are formed.
In the N+-type region 104, a plurality of trenches 106 are formed like stripes extending toward the P+-type region 105 substantially parallel to each other. Each trench 106 penetrates the N+-type region 104 and the P−-type layer 103 under the N+-type region 104. The deepest portion of each trench 106 reaches the N−-type layer 102. In each trench 106, via a gate insulating film 107, a gate electrode 108 made of polysilicon doped with an N-type impurity at a high concentration is embedded.
The surface of the gate electrode 108 is formed lower than the surface of the N+-type region 104. On the gate electrode 108, a tungsten silicide film 109 is formed. The tungsten silicide film 109 fills the inside of the trench 106 and its surface is flush with the surface of the N+-type region 104. Thereby, a polycide structure is formed and lowering in resistance of gate electrode wiring formed by the gate electrode 108 and the tungsten silicide film 109 is realized.
On the N+-type region 104 and the P+-type region 105, an interlayer insulation film is formed although this is not shown. On this interlayer insulation film, a source electrode is formed so as to be contacted by (electrically connected to) the N+-type region 104 and the P+-type region 105 via a contact hole formed in the interlayer insulation film.
On the other hand, on the back surface of the N+-type substrate 101 (surface on the side opposite to the side where the N−-type layer 102 is formed), a drain electrode 110 is formed. By controlling the potential of the gate electrode wiring while applying an appropriate voltage between the drain electrode 110 and the source electrode, a channel is formed in the vicinity of the interface with the gate insulating film 107 in the P−-type layer 103 and a current can be supplied between the drain electrode 110 and the source electrode.
On the gate electrode 108, the tungsten silicide film 109 is formed to lower the resistance of the gate electrode wiring including the gate electrode 108 and the tungsten silicide film 109, whereby an increase in parasitic resistance according to an increase in fineness of the gate electrode wiring can be suppressed.
The tungsten silicide film 109 can be selectively formed on the gate electrode 108 by using processes of both W-CVD and W etch back (or W-CMP). However, if the tungsten silicide film 109 is formed to be thicker than the N+-type region 104 (if the bottom surface of the tungsten silicide film 109 becomes lower than the bottom surface of the N+-type region 104), the threshold voltage of the VDMOSFET deviates from a designed value. Therefore, the tungsten silicide film 109 must be formed to be thinner than the N+-type region 104, and process control for realizing this is difficult.